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4.7.3 INTEL I80-TYPE PARALLEL INTERFACE TIMING
(See Figures 5 and 6)
Item Symbol Min. Max. Unit
RS setup time
tRSS
10
-
ns
RS hold time
tRSH
10
-
ns
Input signal fall time
tf
-15ns
Input signal rise time
tr
-15ns
WR/ pulse width low
tWRL
30
-
ns
WR/ pulse width high
tWRH
100
-
ns
Write data setup time
tDSi
30
-
ns
Write data hold time
tDHi
10
-
ns
WR/ cycle time
tCYCWR
200
-
ns
RD/ cycle time
tCYCRD
200
-
ns
RD/ pulse width low
tRDL
70
-
ns
RD/ pulse width high
tRDH
100
-
ns
Read data delay time
tDDi
-70ns
Read data hold time
tDHRi
580ns
Note: All timing is specified using 20% and 80% of VCC
as the reference points.
RS
WR/
DB0-DB7
t
RSS
t
RSH
t
DSi
t
CYCWR
t
DHi
t
WRL
t
WRH
t
r
t
f
Figure 5.
Intel I80-Type Parallel Interface Write Cycle Timing
9 of 24
M0420SD-204SDAR1-3
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